Due to the continuing miniaturization of structures which are present on semiconductor chips and due to existing cost pressure in mass production of semiconductor chips, new methods and architectures are required to interconnect the semiconductor chips with their structures, which are becoming smaller and smaller, to corresponding structures on circuit boards or to adjacent chips. Here mainly the size difference of structures and connecting lines on the chip compared to conventional structures on circuit boards constitutes a technical problem. The structures of the circuit boards are also being further miniaturized and refined in order to keep up with progress in chip manufacture. Due to the existing cost pressure there is however a demand for use of more favorable circuit boards with bonding structures which have a less fine structure compared to the chip structures. This is because different types of chips, especially chips with different degrees of miniaturization, must be applied to the circuit boards so that in the production of the circuit boards as a result of further miniaturization of the bonding structures economical production would no longer be possible. Chips with a high connection density would determine the choice of circuit board material and the production process for the circuit boards.
Another technical problem is that the circuit boards of conventional design have thermal expansion which is very different from that of semiconductor materials such as silicon and germanium. To prevent the difference in thermal expansion between the circuit board and the semiconductor material from leading to fatigue fracture, in many cases also certain minimum dimensions of the connecting structures (often implemented with so-called bumps consisting of generally eutectic metal alloys) between the chips and the circuit boards must be maintained. For stabilization of chips in chip stacks or on the circuit board moreover fill materials must often be introduced into the gaps; this leads to problems in further miniaturization of the connecting structures.
Among others, due to the aforementioned technical problems chips are produced by so-called fan-out bonding structures. Here a semiconductor chip or chip stack is potted in a fill material which is used to enlarge the base area of the chip and thus to have available more space for connections. The very densely packed terminals on the semiconductor chip are widened on the larger area which consists of the semiconductor chip and the filler material (fan-out). The widened structures can then be connected to the circuit board via bumps.
Existing methods for producing chips with fan-out bonding structures are based on an adhesive, on which the chips are placed, being applied to the carrier. The adhesive is for example an adhesive film which is laminated onto the carrier. The chips are applied to the adhesive film with a pick-and-place tool and are then potted with a layer material (molding compound). After detaching the resulting hybrid wafers from chips and layer material (molding compound) the fan-out bonding structures are produced on the front.
Detachment of the hybrid wafer from the carrier poses technical problems in the existing method, especially due to the above described soluble adhesive connections. Mainly temporary connections are used and the adhesive connections often react with the materials used for potting. In the existing methods therefore special attention must be focused on the adhesives being compatible with the material used for potting of the chips both chemically and mechanically and mainly with respect to the process temperatures which are used.
Due to the carrier materials which have been used and which are conventionally chosen from the group of metals, ceramic, or semiconductor materials, UV-soluble adhesives or adhesives which are dissolved by means of irradiation by a light source, such as for example a laser, are precluded since these carriers are conventionally not transparent to the wavelengths necessary for dissolving the adhesives.
But thermally soluble adhesives such as for example double-sided adhesive tapes or thermally soluble adhesives with thermoplastic behavior also pose technical problems. The adhesives generally do not have the necessary temperature stability which in conventional adhesives generally extends up to 150° Celsius or a maximum 200° C. Celsius. Moreover the adhesives are less resistant to mechanical deformation as the temperature rises, as a result of which chips during potting can slip and in the worst case no longer have any contact with the corresponding bonding terminals. Potting conventionally takes place at a temperature between 150° Celsius and 200° Celsius.
Another problem consists in that many materials which are used for potting are only conditionally compatible with the available temporary adhesives since they interact with the materials used for potting. Therefore it has been necessary so far to qualify the interaction of each individual potting material intended for use with the adhesives which have been used. In this way in practice the amount of usable materials is greatly limited so that reaction to requirements in the production of chips becomes less flexible.
Another problem is in the production of chip stacks which are stacked in several layers of chips and which are to be connected to one another in an electrically conductive manner. The chip stacks, also called 3D packages, have through silicon vias (TSVs) which allow direct stacking and electrical connection of chips. The production of these electrical connections which are in practice generally metallic solder connections or diffusion bonding connections generally requires temperatures beyond 200° Celsius, even partially up to 300° Celsius. At these temperatures all adhesives known at present fail.
Another technical problem is the lack of transparency of most known adhesives with respect to visible light, since in particular when chips are being placed by means of pick and place equipment exact alignment is possible only for correspondingly transparent adhesives. The alignment accuracy therefore suffers in many adhesives so that in special cases so called global alignment is used in which the chips are placed in a predefined grid with the aid of an external reference system (which does not belong to the wafer). Generally this reference system is formed by the stage (holding means) and the sensors of the pick and place system which belong to the stage. This entails the disadvantage that possible thermal expansions of the entire system directly influence the alignment accuracy. As a result, the structure of the pick and place system must be correspondingly durable and stable in order to eliminate these effects and the tendency to a drift of alignment accuracy. This greatly increases costs for alignment.
To the extent a thermal or thermomechanical process is to be used when the hybrid wafer is detached from the carrier, there is the problem that the temperature for the molding compound materials is critical to intolerable here. The materials when heated lose mechanical stability; this makes detachment from the carrier in the heated state at least difficult. Here the alignment accuracy of the individual chips in the grid, which is a prerequisite for further successful processing of the hybrid wafer, can also be adversely affected. For example, in the terminal the very densely packed connecting pads on the individual chips are to be bonded to contacts which are defined by means of lithography in thin film technology. The contacts, which require the finest structure sizes, are delicately the most critical. In other words, the contacts which are provided directly on the chips have the finest resolution and the greatest density compared to the other layers, while the chips have the greatest variation with respect to lateral (X-Y plane) alignment accuracy. The other connecting layers, compared to the first high resolution layer with respect to lateral positioning accuracy of the individual structures, require a much smaller (factor of 2 to a factor of 5) lateral positioning accuracy than the chips.
In summary therefore the problems are as follows:                chemical stability of the adhesives used        thermal stability of the adhesives used        thermomechanical stability of the adhesives used        lack of transparency of the adhesives used (alignment accuracy)        alignment accuracy of chips (floating)        temperature in the detachment process        